Generally, shallow trench isolations (STIs) are used to separate and isolate active areas on a semiconductor wafer from each other. These STIs have historically been formed by etching trenches, overfilling the trenches with a dielectric material such as an oxide, and then removing any excess oxide with a process such as chemical mechanical polishing (CMP) or etching in order to remove the dielectric material outside the trenches. This dielectric material helps to electrically isolate the active areas from each other.
Integrated circuit (IC) technologies are constantly being improved. Such improvements frequently involve scaling down device geometries to achieve lower fabrication costs, higher device integration density, higher speeds, and better performance. Along with the advantages realized from reducing geometry size, improvements are being made directly to the IC devices.
Due to device scaling, improvements to IC devices are continually being made to further improve STIs. Although existing STIs and methods of fabricating STIs have been generally adequate for their intended purposes, as device scaling down continues, they have not been entirely satisfactory in all respects.